NEWS

    7 things you probably do not know about De-RISC Project

    Mar 12, 2021

    Four companies from three different countries are part of the consortium.

    Our consortium is formed by:

    • Fent Innovative Software Solutions (fentISS): Spanish technological company that offers software solutions specifically designed for critical real-time embedded partitioned systems using virtualization techniques.
    • Barcelona Supercomputing Center (BSC): National Supercomputing Facility in Spain whose mission is to research, develop and manage information technologies in order to facilitate scientific progress.
    • Thales Research and Technology (TRT): corporate research centre from Thales located in France. TRT operates a global network of corporate research laboratories, most of which are located on university campuses close to the company’s research partners.
    • Cobham Gaisler: Swedish company which provides space-grade integrated circuits, IP cores and supporting development tools for embedded processors based.

    De-RISC Project is currently a member of RISC-V International and HiPEAC network.

    We feel very proud of being part of these two organizations. RISC-V International is a global nonprofit association whose mission is to promote RISC-V, a free and open ISA that enables a new era of processor innovation through open standard collaboration. On the other hand, HiPEAC (European Network on High-performance Embedded Architecture and Compilation) network consists of a European network which provides a platform for cross-disciplinary research collaboration, promoting the transformation of research results into products and services.

    You can check both of our De-RISC pages in the following links:

    • De-RISC – RISC-V International
    • De-RISC – HiPEAC network

    Over the first half of the project, the consortium has participated in a total of 17 conferences, workshops or seminars.

    During its the first half of the project, De-RISC has participated in 17 events in different locations across Europe:

    • The 1st RISC-V week 2020
    • 13th ESA Workshop on Avionics, Data, Control and Software Systems (ADCSS)
    • 3rd BRAVE FPGA User Day
    • GR740 User Day
    • TEC-ED & TEC-SW Final Presentation Days
    • HiPEAC 2020
    • TRT internal dissemination event about H2020 projects
    • Design, Automation and Test in Europe Conference (DATE 2020)
    • IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2020)
    • Internal Workshop LVCUGEN
    • RISC-V Global Forum
    • Industry Space Days (ISD 2020)
    • European Research and Innovation Days
    • RADECS 2020  
    • Journée de Palaiseau Open Computing
    • RISC-V Summit 2020
    • HIPEAC Conference 2021

    If you want to keep track of the events in which De-RISC participates, follow the official Twitter and LinkedIn page!

    The colors of De-RISC’s logotype match the ones from RISC-V International.

    The De-RISC communication team wanted to highlight the great connection between the project and RISC-V and this was a great graphic way of doing it. Dark blue and gold yellow are the colours chosen and they are present in any visual material of this ambitious H2020 Project.

    The full De-RISC architecture will be validated with three use cases.

    In order to test the full De-RISC architecture, three use-cases will validate the features of the NOEL-V processor and XtratuM Next Generation (XNG): a low-level benchmark execution, an on-board satellite software stack, and a command & data handling subsystem.

    The execution of low-level benchmarks will validate the basic functionality of the architecture and will provide simple performance estimation to compare the architecture performance to other solutions available on the market.

    The on-board satellite software stack will use LVCUGEN, a generic on-board framework developed by CNES using XtratuM and LithOS. The purpose of this framework is to provide common on-board functions which are re-usable for different missions to minimize the satellite integration effort and ease the testing activities.

    The last use case will be a Command & Data Handling subsystem, whose purpose is to evaluate the usage of multi-core processors in the context of mini- and micro-satellite constellations. 

    You can find more details about these three use cases in the De-RISC Use Cases section. 

    An official presentation is regularly updated and it is available for its download.

    The consortium has created an official presentation in order to facilitate the dissemination process of the project. This document gives a great overview of the project and its current progress. The latest version of this document is available on the Branding section of the website for its public download.

    De-RISC has successfully achieved the first half of the project duration.

    Time flies, right? De-RISC started in October 2019 and is expected to conclude in March 2022. During this first half of the project, all our team members have worked really hard to make De-RISC a reality. As a result, the project progresses as it is expected and it has already achieved most of its KPIs. Our team is very proud of the performance of the full consortium during these past months and will continue working on De-RISC just as well!