Ada User Journal 2020, Vol41(2)
The space domain demands increased performance, reliable and easy to verify and validate platforms to match the requirements of highly autonomous missions and systems that need to undergo qualification and certification against safety guidelines, and be commercialized worldwide minimizing export restrictions. Unfortunately, commercial platforms either fail to match domainspecific requirements for space (e.g. safety requirements), are limited by US export regulations, or simply fail both sets of requirements. This paper introduces De-RISC, a novel HW/SW platform meeting space requirements for safety- and mission-critical applications by construction, with explicit support to ease performance validation and diagnosis, and based on the RISC-V instruction set architecture. The De-RISC platform, which builds upon fentISS’ XtratuM hypervisor and a Cobham Gaisler (CG) NOEL-V based MPSoC, will reach commercial maturity in 2022, and will be assessed against a space use case.
Citation: Gómez F., Masmano M., Nicolau V., Andersson J., Le Rhun J., Trilla D., Gallego F., Cabo G., Abella J. De-RISC – Dependable Real-Time Infrastructure for Safety-Critical Computer Systems. Ada User Journal. 2020, Vol41(2), pp.107-112.
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SafeSU: an extended statistics unit for multicore timing interference
Statistics units (SUs) in MPSoCs are becoming increasingly used for the (1) verification and (2) validation of multicore timing interference, as well as for (3) deploying safety measures in safety-related real-time systems. However, existing SU extensions to manage multicore timing interference have neither been integrated together nor deployed in commercial MPSoCs.This paper presents the realization of the Safe Statistics Unit (SafeSU for short), which smartly integrates existing solutions for multicore timing interference verification, validation and monitoring, and is in turn integrated in commercial space-graded RISC-V and SparcV8 MPSoCs. Our evaluation illustrates the operation of the SafeSU, and paves the way for a thorough validation prior to reaching commercialization and being offered as open source IP.
Citation: Cabo, G. [et al.]. SafeSU: an extended statistics unit for multicore timing interference. A: IEEE European Test Symposium. "2021 IEEE European Test Symposium, ETS 2021: May 24-28, 2021, Belgium: Proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2021, p. 1-4. ISBN 978-1-6654-1849-2. DOI 10.1109/ETS50041.2021.9465444.
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De-RISC: the First RISC-V space-grade platform for safety-critical systems
The increasing needs for performance in the space domain for highly autonomous systems calls for more powerful space MPSoCs and appropriate hypervisors to master them. These platforms must adhere to strict reliability, verifiability and validation requirements since spacecraft for deep space missions are exposed to a harsh environment. Systems must undergo screening and tests against standards for electronic components and software. Unfortunately, currently available space-grade processor components do not meet requirements related to safety that are becoming increasingly important in space applications. This paper presents the De-RISC platform, consisting of Cobham Gaisler’s RISC-V based SoC, and fentISS’ XtratuM Next Generation hypervisor. The platform implements the open RISC-V Instruction Set Architecture, and leverages space SoC IP by Cobham Gaisler, space hypervisor technology by fentISS, multicore interference management solutions by the Barcelona Supercomputing Center, and end user experience and requirement guidance by Thales Research and Technology. At its current state, the platform is already complete and integrated, and starting its validation phase prior to reaching commercial maturity by early 2022. In this paper, we provide details of the platform and some preliminary evidence of its operation.
Citation: Wessman, N. [et al.]. De-RISC: the First RISC-V space-grade platform for safety-critical systems. A: IEEE Space Computing Conference. "2021 IEEE Space Computing Conference: 23-26 August 2021, virtual (online): proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2021, p. 17-26. ISBN 978-1-6654-2400-4. DOI 10.1109/SCC49971.2021.00010.
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De-RISC: Launching RISC-V into space
An important challenge faced by mission-critical computers is the ability to scale the processing performance, while maintaining a high level of dependability in a harsh environment. The adoption of COTS multi-core processors, as in non-critical industries, poses difficulties both in terms of timing interference due to concurrent access to shared hardware resources, and reliability under thermal and radiation stress.
Specific dependability-related features are thus required for space computers. In this domain, the LEON processors are a European success-story, adopting an open architecture, being available as open-source implementations to allow validation by a wide user base, and having fault-tolerant implementations available to support missions with high-reliability requirements. The recent RISC-V open-source instruction set architecture is a great opportunity to push this concept further, with a renewed potential for growth and wide adoption.
The De-RISC project (Dependable Real-time Infrastructure for Safety-critical Computer) aims at providing the first complete processing platform for space, leveraging RISC-V cores and state-of-the-art hypervisor technology. The platform is composed of an FPGA-based SoC with high-performance NOEL-V cores, minimized interference channels and many space-grade peripherals. The SoC platform hosts both the XtratuM Next Generation (XNG) hypervisor and LithOS guest operating system for applications isolation and scheduling. In addition, the platform implements advanced monitoring techniques that help to ensure the real-time behaviour in a multicore context.
In order to validate the platform, in addition to basic benchmarks and tests, a realistic space use-case will be deployed, based on the LVCUGEN (Logiciel de Vol Charge Utile GENerique) framework, the CNES generic payload software based on Time & Space Partitioning. WIth the CCSDS123 hyperspectral image compression as a high-throughput application and TM/TC communications as low-latency critical application, it covers a complete mixed-critical system.
The current status of the project is in line with the plans: the prototype platform is already functional and almost complete, with new features added in scheduled internal releases. The validation phase has started, and will proceed incrementally until the end of the project. The commercial release of the platform is expected for Q2 2022.
Citation: Jimmy Le Rhun, Vicente Nicolau, Antonio Garcia-Vilanova, Jan Andersson, & Sergi Alcaide. (2021, June 14). De-RISC: Launching RISC-V into space. OBDP2021 - 2nd European Workshop on On-Board Data Processing (OBDP2021). https://doi.org/10.5281/zenodo.5575008
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De-RISC: Dependable Real-time RISC-V Infrastructure for Safety-critical Space and Avionics Computer Systems
The world market for aviation and space computing systems faces a significant shift caused by the loss of momentum of the traditionally used PowerPC and SPARC instruction set architectures in the commercial domain. This means that the space industry is not able to leverage training, software tools, etc. from the commercial domain and this fuels a need to shift to architectures present in larger commercial markets.
The De-RISC project brings together leading European entities within the areas of fault-tolerant microprocessors, hypervisors, embedded safety-critical software and mixed-criticality systems in an effort to commercialize a complete technology stack consisting of an FPGA space grade development board, system-on-chip design and software stack. The goal is to create a platform for the
aerospace industries implementing the open RISC-V microprocessor instruction set architecture together with specific features to address the needs of the target industries and to adopt modern commercial technology to allow leveraging technology development from other domains.
Citation: Gómez-Molinero, Francisco, Masmano, Miguel, Nicolau, Vicente, Wessman, Nils-Johan, Andersson, Jan, Le Rhun, Jimmy, Cabo, Guillem, Benedicte, Pedro, Alcaide, Sergi, & Abella, Jaume. (2021, September 22). De-RISC: Dependable Real-time RISC-V Infrastructure for Safety-critical Space and Avionics Computer Systems. DATA SYSTEMS IN AEROSPACE 2021 (DASIA). https://doi.org/10.5281/zenodo.5707537
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De-RISC: A complete RISC-V based space-grade platform
The H2020 EIC-FTI De-RISC project develops a RISC-V space-grade platform to jointly respond to several emerging, as well as longstanding needs in the space domain such as: (1) higher performance than that of monocore and basic multicore space-grade processors in the market; (2) access to an increasingly rich software ecosystem rather than sticking to the slowly fading SPARC and PowerPC-based ones; (3) freedom (or drastic reduction) of export and license restrictions imposed by commercial ISAs such as Arm; and (4) improved support for the design and validation of safety-related real-time applications, (5) being the platform with software qualified and hardware designed per established space industry standards. De-RISC partners have set up the different layers of the platform during the first phases of the project. However, they have recently boosted integration and assessment activities. This paper introduces the De-RISC space platform, presents recent progress such as enabling virtualization and software qualification, new MPSoC features, and use case deployment and evaluation, including a comparison against other commercial platforms. Finally, this paper introduces the ongoing activities that will lead to the hardware and fully qualified software platform at TRL8 on FPGA by September 2022.
Citation: Wessman, N. [et al.]. De-RISC: A complete RISC-V based space-grade platform. A: Design, Automation and Test in Europe Conference and Exhibition. "Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE 2022): 14-23 March 2022, online virtual platform". Institute of Electrical and Electronics Engineers (IEEE), 2022, p. 802-807. ISBN 978-3-9819263-6-1. DOI 10.23919/DATE54114.2022.9774557.
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