The De-RISC consortium is formed by 4 organizations from 3 different European countries (Spain, Sweden and France) which bring together the necessary competence and critical mass in terms of expertise and resources to ensure the achievement of the project goals and the impact of the project results at European level.

FentISS has developed qualified (ECSS level B) versions of their hypervisor, XtratuM, running in ARM processors and in LEON processors (monocore) that are currently flying in several dozens of satellite missions. In the forthcoming years they will multiply its presence in the space reaching up to 700 satellites orbiting Earth. This version of XtratuM will be ported to the RISC-V multicore architecture developed in the project and it will be validated to aerospace standards within this scope.

The Barcelona Supercomputing Center – Centro Nacional de Supercomputación, member of the RISC-V foundation, has already ported some innovative multicore technologies aimed to ease software verification to existing open-source RISC-V platforms and will integrate, in the context of De-RISC, these solutions in the RISC-V-based MpSoC system of Cobham Gaisler

Cobham Gaisler, member of the RISC-V foundation, has developed a RISC-V based platform that merges peripherals (communication controllers) from current space systems together with RISC-V processor implementations. The intent of the proposed work is to leverage this development and productise a RISC-V-based MPSoC system including a RISC-V processor implementation from CG by raising their TRL to 8.

Thales Research & Technology, a major European leader in the aerospace industry, is also a member of the RISC-V Foundation. During the project, it will validate the RISC-V multicore hardware/software platform in a realistic use-case, introducing on-board space and aviation requirements from the start, as well as ensuring the alignment of the developed technology with the European space industry needs.