BSC’s SafeSU, part of De-RISC, is a powerful multicore-interference oriented statistics unit allowing to monitor and control how much contention each core (or master) causes on each other. One of its key features is its ability to set quotas to multicore interference (contention) and report it back to the software layers through appropriate interrupts.
In De-RISC project, contention control features of the SafeSU are integrated in the AMBA AHB main bus, thus allowing to limit how much this component is used by each core. This is particularly useful to prevent both unintended overuse of the bus as well as denial-of-service attacks based on flooding. The former is of particular relevance for safety, since it allows preventing mixed-criticality issues if a low-criticality task produces excessive interference on a higher-criticality one. The latter is key to deal with security concerns if any attacking software manages to access the platform and generate interference with the purpose of saturating some specific hardware resources.
This mechanism, which is already integrated in the De-RISC MPSoC, will be thoroughly validated during forthcoming months. Moreover, a fully-portable version of the SafeSU including contention control features will be released in the next few months and integrated as part of an industrial-relevant platform for the edge domain as part of the ECSEL FRACTAL project to further increase exploitation opportunities.
Guillem Cabo, Francisco Bas, Ruben Lorenzo, David Trilla, Sergi Alcaide, Miquel Moreto, Carles Hernandez, Jaume Abella, “SafeSU: an Extended Statistics Unit for Multicore Timing Interference”, 36th IEEE European Test Symposium (ETS), 2021, https://people.ac.upc.edu/jabella/ETS21.pdf