Extended SafeSU for L2-DRAM interference

May 12, 2022

BSC’s safe statistics monitoring unit, the SafeSU, part of De-RISC, is a powerful multicore-interference oriented statistics unit allowing to monitor and control how much contention each core (or master) causes on each other.

However, to monitor the contention, the appropriate signals need to be created and fed to the SafeSU to ensure that the unit is aware of all contention. To achieve it, BSC is preparing different controlled configuration setups of benchmarks to stress the memory hierarchy and validate that the contention reported by the SafeSU matches with the expectation.

In this process, BSC’s researchers have noticed that the L2-DRAM interface is a key element to monitor contention, especially during write transactions producing L2 misses. In order to measure contention correctly, certain signals are propagated to the SafeSU and transactions between the two main buses of the system are checked. Results for controlled cases so far reflect that contention measured by the SafeSU closely matches expectations.