Hints from multicore validation tests

Sep 24, 2021

Validation is a crucial phase in the development of a product, especially in safety-critical systems.

As part of the validation plan, BSC is in charge of the multicore interference validation tests. In these tests, the different processing elements (NOEL-V CPUs) of the De-RISC SoC are loaded with different precompiled binaries to observe how interference occurs when accessing the shared resources.

Multicore tests are designed with a preceding hypothesis of which binaries will regularly access the shared resources and will create more contention. With this, SafeSU – BSC’s interference aware statistics unit – measurements can be later compared against the hypothesis by accounting for the contention observed against the increase in execution time with respect to the isolation test.

The current design of the multicore interference validation tests includes both low-level designed stressing benchmarks as well as state-of-the-art benchmark suites such as EEMBC AutoBench or TacleBench purposedly ported into RISC-V for these tests. Preliminary results indicate that the contention measured by the SafeSU is not all the contention that the core under test is suffering, which indicates that contention is occurring in more than one shared resource. More importantly, these results confirm the appropriateness of the tests designed. Additional observability channels are being investigated to observe such contention, hence making the platform more diagnosis-friendly.