Hardware performance monitoring counters (PMCs) are a set of special-purpose registers used to count specific hardware events in CPUs.
PMCs can be used to count cache events such as cache accesses or cache misses. Traditionally PMCs have been used as an observability channel for low-level average performance evaluation and optimization of applications, as well as for debug purposes.
In De-RISC project, a more powerful statistics unit, SafeSU, has been designed. BSC has devised a performance monitoring unit particularly intended to manage multicore timing interference by providing specific observability and controllability channels that can be used for the verification, validation and safety measure implementation in safety-related real-time systems.
For instance, the SafeSU allows monitoring the multicore contention suffered in shared resources, assign quotas for shared resource access to cores, or measure the duration of specific events to those shared resources. In particular, the De-RISC SafeSU includes the CCS (Contention Cycle Stack) , the MCCU (Maximum Contention Control Unit) [2r], and the RDC (Request Duration Counter) .
The CCS is a set of counters that monitor the exact contention (in cycles) a given core causes on each other core based in the access to shared resources. The CCS can be used to validate timing budgets, and diagnose the causes of deadline overruns.
The MCCU controls the amount of contention caused by each core on each other core in the access to shared resources by allowing to set contention quotas to cores, raising an interrupt whenever a quota is exceeded. The MCCU can be built on top of the CCS to monitor contention experienced and caused by cores and compare it against user-defined quotas.
The RDC is a mechanism to record the maximum duration of each request type to shared resources, and can be set to raise an interrupt if a particular watermark is exceeded.
J. Jalle et al., “Contention-aware performance monitoring counter support for real-time MPSoCs,” 2016 11th IEEE Symposium on Industrial Embedded Systems (SIES), Krakow, Poland, 2016, pp. 1-10, doi: 10.1109/SIES.2016.7509440.
 J. Cardona, C. Hernandez, J. Abella and F. J. Cazorla, “Maximum-Contention Control Unit (MCCU): Resource Access Count and Contention Time Enforcement,” 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, Italy, 2019, pp. 710-715, doi: 10.23919/DATE.2019.8715155.