NEWS

The De-RISC MPSoC includes BSC‘s SafeSU, a statistics unit implementing several features related to multicore interference validation, diagnostics, and safety measures support. However, SafeSU’s features are effective as long as contention occurs in the AHB bus, where it is connected. If the corresponding slave accepts requests and those are delayed in internal queues without keeping the AHB bus busy, then such contention is not exposed to the SafeSU. This is the case for part of the contention in the De-RISC MPSoC whenever write requests keep DRAM memory busy, delaying further write requests.

Hence, as part of De-RISC, BSC is in the process of extending the SafeSU to monitor the L2-to-DRAM bus connecting the L2 cache with the DRAM controller and detect when a request takes longer than the minimum service time to be served to report such interference. Such extension is expected to be completed during Q1 2022 and offered as open-source along with the original SafeSU already released.