-
No US export restriction
-
Multi-core interference migration
-
Portability
-
Fault-tolerance
-
Open standards
| 1 |
Strengthen European leadership in the supply of Integrated Modular Avionics HW/SW. |
| 2 |
Consolidate the European position in real-time embedded processors technology. |
| 3 |
Capitalize on the economy of scale by reinforcing an open standard Instruction Set Architecture (ISA) for the embedded market. |
LATEST NEWS
De-RISC Project gets presented at HIPEAC 2022
The HiPEAC conference is the premier European forum for experts in computer architecture, programming models, compilers and operating systems for embedded and general-purpose systems. This last week, De-RISC representatives participated in the 17th...
Extended SafeSU for L2-DRAM interference
BSC’s safe statistics monitoring unit, the SafeSU, part of De-RISC, is a powerful multicore-interference oriented statistics unit allowing to monitor and control how much contention each core (or master) causes on each other. However, to monitor the contention, the...
10th progress meeting
On April 21st 2022, all partners from De-RISC consortium attended the 10th progress meeting of the project and went through the different work packages, sharing all the advances and results obtained during these past months. Each...
