The validation of the De-RISC platform involves several end-user use-case applications, representative of aerospace scenarios.
The first use-case which will be developed in De-RISC Project is in fact composed of a series of small benchmarks and applications, in order to assess the raw performance of the platform, its compliance with the RISC-V standard, and the effectiveness of the timing interference mitigation techniques developed in the project.
A first step has been to use standard benchmark applications such as Dhrystone or EEMBC Coremark, in order to confirm the high performance of the dual-issue NOEL-V core, reaching 2.82 DMIPS/MHz and 4.41 Coremark/MHz on the current version of the prototype platform.
These benchmarks are useful for core-level evaluation and comparison with other implementations, but as they fit in first-level cache memories, they do not really test the memory hierarchy. Therefore, we also use a collection of computation kernels, such as matrix multiplication, FFT, SHA-1 etc. to evaluate the real-world performance, taking data throughput into account.
An important challenge for dependable multicore processors is the presence of timing interference, i.e. delays incurred by an application when there is a concurrent access to a shared hardware resource. The De-RISC platform is designed to minimize such interferences. In order to confirm the effectiveness of the techniques developed in the project, another set of micro benchmarks is developed, thanks to BSC’s know-how in this domain, to selectively stress hardware resources with repeated access, and measure the impact on a reference benchmark execution time.
Overall, this collection of basic benchmarks will give a good baseline of the performance and the determinism of the De-RISC hardware platform and its unique set of features.