Get to know De-RISC’s team!

Oct 22, 2020

Good teamwork is essential in all organizations. It means that people are working towards a shared purpose and common goals. Cooperation is a key factor on this topic and it becomes essential when different organizations are involved in a project. The De-RISC team is made up of great professionals from four different companies who work really hard to make the project successful. Here is a brief insight of some of them!

Paco Gómez (FEN)

Project coordinator of De-RISC and WP6 and WP7 leader. He is in charge of the reporting to the EU, the coordination of project activities, chairing the Project Executive Board and leading the exploitation and business plan activities for fentISS.

Vicente Nicolau (FEN)

Project manager and WP5 leader. He is in charge of the communication and dissemination strategy of the project, as well as the management of it. He also contributes to WP3 and WP6 with minor tasks. 

Miguel Masmano (FEN)

WP3 leader. He leads the technical work on fentISS side and is in charge of the software tasks, specifically work related with the XtratuM hypervisor.

Jaume Abella-Ferrer (BSC)

Executive Board from BSC and senior researcher. He supervises De-RISC execution on the BSC side, supporting David Trilla in the technical coordination and strategy for the integration and testing of hardware solutions for time predictability and validation.

David Trilla (BSC)

Post-doc researcher and the technical coordinator of BSC’s efforts in the project with support from Jaume Abella. He manages the BSC team to guide the implementation and integration of new hardware solutions for time predictability and timing interference mitigation. 

Dayana Fernandes Muzzeto (BSC)

Leader of dissemination and communication tasks on BSC. She is involved in the De-RISC project to support its dissemination and communication objectives. Her aim is to create awareness of De-RISC technology by reaching targeted audiences.

Jimmy Le Rhun (TRT)

Executive board from Thales Research & Technology and WP1 leader. He manages TRT’s  contribution to the project and organizes the collection of requirements for the De-RISC platform. In relation with end-users, he coordinates the adaptation of space-grade applications for the validation of the system.

Rieul Ducousso (TRT)

PhD student working with Thales Research & Technology. He is working on issues related to I/O security in embedded RISC-V systems. He is involved in the development and validation of an IOMMU for safety-critical systems.

Jérôme Quévremont (TRT)

He cross-coordinates RISC-V and open hardware related activities at Thales Research & Technology. He also chairs the special interest group Functional Safety (SIG-Safety) at RISC-V International (formerly RISC-V Foundation) which is attended by some De-RISC participants

Jan Andersson (CG)

Executive Board from Cobham Gaisler and WP2 and WP4 leader. He is in charge of the correct development of De-RISC at Cobham Gaisler and is responsible for the hardware platform integration work.

Fabio Malatesta (CG)

Design Engineer. He works with verification of the NOEL-V processor core and digital design work on the De-RISC system-on-chip design.

Nils-Johan Wessman (CG)

Senior Design Engineer and lead developer for the NOEL-V microprocessor core. He leads the extension work on the processor core within De-RISC and supports the creation of the system-on-chip hardware platform.