Validation plans specify the information related to the validation of the project. This process led by Barcelona Supercomputing Center (BSC) constitutes a key step on the De-RISC project.
As De-RISC technologies gain maturity, there is an increasing need for starting the validation phase. During the last months, BSC has elaborated a detailed plan for the performance validation of the Cobham Gaisler’s NOEL-V based SoC as a first step prior to validating the integrated software stack, with fentISS’ XtratuM hypervisor and Thales’ use case.
This SoC bare-metal validation builds upon micro-benchmarks’ BSC technology and also benchmarks from relevant benchmark suites. Tests have been devised both to test that no unintended interference channels exist and that known ones behave as expected, i.e., with varying relative impact in execution time and, in all cases, with fairness across contender cores.
In particular, 30 multicore tests based only on micro-benchmarks have been devised to test the sensitivity of read and write access streams to the different levels of the memory hierarchy when different types of interference occur in those levels of the memory hierarchy. Regarding regular benchmarks, test templates have been defined to generate multicore workloads as the last set of bare-metal tests.
As soon as all partners approve the validation plan, test batteries will be run and results assessed to validate the SoC’s performance characteristics and, eventually, spot corner cases that may need SoC enhancements.
Overall, the start of the validation phase takes De-RISC partners to the second and final phase of the project, where technology integration and verification are complete, and TRL8 is successfully achieved through extensive test campaigns.