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De-RISC Project gets presented at HIPEAC 2022
The HiPEAC conference is the premier European forum for experts in computer architecture, programming models, compilers and operating systems for embedded and general-purpose systems. This last week, De-RISC representatives participated in the 17th...
Extended SafeSU for L2-DRAM interference
BSC’s safe statistics monitoring unit, the SafeSU, part of De-RISC, is a powerful multicore-interference oriented statistics unit allowing to monitor and control how much contention each core (or master) causes on each other. However, to monitor the contention, the...
10th progress meeting
On April 21st 2022, all partners from De-RISC consortium attended the 10th progress meeting of the project and went through the different work packages, sharing all the advances and results obtained during these past months. Each...
Full virtualization in De-RISC
Virtualization is an operating system paradigm in which the system kernel enables the hosting of multiple isolated computer systems on a single physical computer system. These virtual computer systems are often called virtual machines or partitions. The ability to...
Steady progress of De-RISC integration and validation activities
On the hardware side, the new pipelined high-performance Floating-Point Unit (FPU) delivered by Cobham Gaisler is working fine, with a 7x increase in floating-point performance compared to the previously integrated area-optimized NanoFPU. The support for...
De-RISC collaboration with SELENE
De-RISC development in the last months is being more than acceptable and the consortium has great expectations with the current and future results. As of today, the consortium has achieved several progress and partners are searching new ways of collaboration such as...
Availability of De-RISC FPGA Board
The De-RISC project develops a platform consisting of the fentISS XNG hypervisor running on a multi-processor system-on-chip design with the NOEL-V RISC-V processor. The project has developed the hardware/software stack using FPGA implementations of the system-on-chip...
De-RISC’s 9th progress meeting
De-RISC consortium starts 2022 with its first 9th progress meeting. Members of the consortium reviewed the current status of the planned activities on the last quarter. Once again, this meeting had to be held online due to the COVID-19 restrictions...
SafeSU integration in De-RISC
The De-RISC MPSoC includes BSC's SafeSU, a statistics unit implementing several features related to multicore interference validation, diagnostics, and safety measures support. However, SafeSU's features are effective as long as contention occurs in the AHB bus, where...
De-RISC consortium participates in RISC-V Summit 2021
The event was held at Moscone West in San Francisco from December 6-8, 2021, and featured hybrid in-person and virtual activities to connect with a global audience. On December 6th to 8th, De-RISC project was represented at RISC-V Summit 2021 to communicate the...
Health monitor in De-RISC
The XtratuM Next Generation (XNG) software incorporates the latest hypervisor services developed by fentISS to match the needs of safety-critical systems. Specifically, the Health Monitor (HM) service detects faults in the hardware and in XNG itself, and responds...
De-RISC’s progress meeting after two years of execution
De-RISC consortium met virtually at their eighth progress meeting to discuss the progress carried out in the last months. On November 26th 2021, all partners from De-RISC consortium attended the 8th progress meeting of the project and went through the...
De-RISC celebrates its second anniversary
The De-RISC Project celebrates its second year through the introduction of a market-ready hardware-software platform based on the RISC-V instruction set architecture (ISA), productizing a multi-core RISC-V system-on-chip and an efficient time and space partitioning...
De-RISC project gets presented at DASIA 2021
DASIA is an annual conference organised by Eurospace since 1996 considered as one of the most important events in the space community. It gathers space data systems specialists over 3 days for presentations, workshops/panels and discussion. It provides...
Hints from multicore validation tests
Validation is a crucial phase in the development of a product, especially in safety-critical systems. As part of the validation plan, BSC is in charge of the multicore interference validation tests. In these tests, the different processing elements (NOEL-V CPUs) of...